The present invention generally relates to semiconductor logic circuits, and more particularly to a semiconductor logic circuit comprising a circuit such as a flip-flop circuit which carries out a clocked operation responsive to a clock pulse.
In a circuit such as a pre-scaler or the like which is applied with a high-frequency signal, there is a demand that the operating speed of the circuit is high as much as possible. For this reason, the high-frequency signal is amplified and shaped in a clock driver circuit and thereafter supplied to a flip-flop circuit.
FIG. 1 shows an example of a conventional semiconductor logic circuit. The semiconductor logic circuit comprises a clock driver circuit 11 and a flip-flop circuit 12. According to this circuit, it is possible to sufficiently drive the clock input to the flip-flop circuit 12 which is provided in a stage next to the clock driver circuit 11, because the high-frequency signal is amplified and shaped in the clock driver circuit 11. Accordingly, the flip-flop circuit 12 can operate at a high speed.
In the conventional semiconductor logic circuit, an output logic amplitude of the clock driver circuit 11 is desirably set to a large value in view of the noise margin, and is set to 800 mV, for example. An interval logic amplitude of the flip-flop circuit 12 is also set to 800 mV by considering the circuit matching with the clock driver circuit 11. However, recently, the clock driver circuit 11 and the flip-flop circuit 12 are built within a large scale integrated circuit, and the noise margin is improved. As a result, it has become possible to set the output logic amplitude of the clock driver circuit 11 to a value smaller than 800 mV. But in this case, the internal logic amplitude of the flip-flop circuit 12 is still set equal to the output logic amplitude of the clock driver circuit 11 by considering the circuit matching.
Therefore, in the conventional semiconductor logic circuit, there is a problem in that the speed of the clocked operation of the flip-flop circuit 12 cannot be further increased, since the internal logic amplitude of the flip-flop circuit 12 is set equal to the output logic amplitude of the clock driver circuit 11 by considering only the circuit matching.